Stratix Architecture
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See Figure 2–28. A single
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block is less than or equal to
2K bits in size.
Figure 2–28. Single-Port Mode Note (1)
8 LAB Row
Clocks
RAM/ROM
8
256 × 16
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
data[ ]
D
ENA
Q
Data In
To MultiTrack
Interconnect
Data Out
D
Q
ENA
address[ ]
wren
Address
D
Q
ENA
Write Enable
outclken
D
ENA
Q
inclken
inclock
Write
Pulse
Generator
outclock
Note to Figure 2–28:
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Altera Corporation
July 2005
2–51
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
