Stratix Architecture
Figure 2–8. Carry Select Chain
LAB Carry-In
0
1
LAB Carry-In
Carry-In0
Sum1
Sum2
Sum3
Sum4
Sum5
A1
B1
LE1
LE2
LE3
LE4
LE5
Carry-In1
A2
B2
LUT
LUT
data1
data2
Sum
A3
B3
A4
B4
LUT
LUT
A5
B5
0
1
Carry-Out0
Carry-Out1
Sum6
Sum7
Sum8
Sum9
Sum10
A6
B6
LE6
LE7
LE8
LE9
A7
B7
A8
B8
A9
B9
A10
B10
LE10
LAB Carry-Out
Clear & Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT-
gate push-back technique. Stratix devices support simultaneous preset/
Altera Corporation
July 2005
2–13
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
