Digital Signal Processing Block
Figure 2–36. 36 × 36 Multiply Mode
signa (1)
signb (1)
aclr
clock
ena
A[17..0]
B[17..0]
D
Q
Q
ENA
D
Q
ENA
CLRN
CLRN
D
ENA
CLRN
A[35..18]
B[35..18]
D
Q
Q
Data Out
D
Q
ENA
D
Q
ENA
ENA
36 × 36
Multiplier
Adder
CLRN
CLRN
CLRN
D
signa (2)
signb (2)
ENA
CLRN
A[35..18]
B[17..0]
D
Q
Q
ENA
D
Q
ENA
CLRN
CLRN
D
ENA
CLRN
A[17..0]
D
Q
Q
ENA
D
Q
ENA
CLRN
CLRN
B[35..18]
D
ENA
CLRN
Notes to Figure 2–36:
(1) These signals are not registered or registered once to match the pipeline.
(2) These signals are not registered, registered once, or registered twice for latency to match the pipeline.
2–66
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1