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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
C8 interconnects span eight LABs, M512, or M4K blocks up or down from  
a source LAB. Every LAB has its own set of C8 interconnects to drive  
either up or down. C8 interconnect connections between the LABs in a  
column are similar to the C4 connections shown in Figure 2–11 with the  
exception that they connect to eight LABs above and below. The C8  
interconnects can drive and be driven by all types of architecture blocks  
similar to C4 interconnects. C8 interconnects can drive each other to  
extend their range as well as R8 interconnects for column-to-column  
connections. C8 interconnects are faster than two C4 interconnects.  
C16 column interconnects span a length of 16 LABs and provide the  
fastest resource for long column connections between LABs, TriMatrix  
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross M-  
RAM blocks and also drive to row and column interconnects at every  
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and  
R4 interconnects and do not drive LAB local interconnects directly.  
All embedded blocks communicate with the logic array similar to LAB-  
to-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks)  
connects to row and column interconnects and has local interconnect  
regions driven by row and column interconnects. These blocks also have  
direct link interconnects for fast connections to and from a neighboring  
LAB. All blocks are fed by the row LAB clocks, labclk[7..0].  
Altera Corporation  
July 2005  
2–19  
Stratix Device Handbook, Volume 1  
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