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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Device Family Data Sheet  
Chapter  
Date/Version  
Changes Made  
4
Table 4–48 on page 4–30: added rows tM512CLKSENSU and tM512CLKENH,  
and updated symbol names.  
Updated power-up current (ICCINT) required to power a Stratix  
device on page 4–17.  
Updated Table 4–37 on page 4–22 through Table 4–43 on  
page 4–27.  
Table 4–49 on page 4–31: added rows tM4KCLKENSU, tM4KCLKENH  
,
tM4KBESU, and tM4KBEH, deleted rows tM4KRADDRASU and tM4KRADDRH, and  
updated symbol names.  
Table 4–50 on page 4–31: added rows tMRAMCLKENSU, tMRAMCLKENH  
tMRAMBESU, and tMRAMBEH, deleted rows tMRAMADDRASU and  
tMRAMRADDRH, and updated symbol names.  
,
Table 4–52 on page 4–34: updated table, deleted “Conditions”  
column, and added rows tXZ and tZX  
Table 4–52 on page 4–34: updated table, deleted “Conditions”  
column, and added rows tXZ and tZX  
Table 4–53 on page 4–34: updated table and added rows tXZPLL and  
tZXPLL  
.
.
.
Updated Note 2 in Table 4–53 on page 4–34.  
Table 4–54 on page 4–35: updated table, deleted “Conditions”  
column, and added rows tXZPLL and tZXPLL  
.
Updated Note 2 in Table 4–54 on page 4–35.  
Deleted Note 2 from Table 4–55 on page 4–36 through Table 4–66 on  
page 4–41.  
Updated Table 4–55 on page 4–36 through Table 4–96 on  
page 4–56. Added rows TXZ, TZX, TXZPLL, and TZXPLL.  
Added Note 4 to Table 4–101 on page 4–62.  
Deleted Note 1 from Table 4–67 on page 4–42 through Table 4–84 on  
page 4–50.  
Added new section “I/O Timing Measurement Methodology” on  
page 4–60.  
Deleted Note 1 from Table 4–67 on page 4–42 through Table 4–84 on  
page 4–50.  
Deleted Note 2 from Table 4–85 on page 4–51 through Table 4–96 on  
page 4–56.  
Added Note 4 to Table 4–101 on page 4–62.  
Table 4–102 on page 4–64: updated table and added Note 4.  
Updated description of “External I/O Delay Parameters” on  
page 4–66.  
Added Note 1 to Table 4–109 on page 4–73 and Table 4–110 on  
page 4–74.  
Updated Table 4–103 on page 4–66 through Table 4–110 on  
page 4–74.  
Deleted Note 2 from Table 4–103 on page 4–66 through Table 4–106  
on page 4–69.  
Added new paragraph about output adder delays on page 4–68.  
Updated Table 4–110 on page 4–74.  
Added Note 1 to Table 4–111 through Table 4–113 on page 4–75.  
Altera Corporation  
Section I–5  
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