Stratix Architecture
Table 2–22. Fast PLL Port I/O Standards (Part 2 of 2)
Input
I/O Standard
INCLK
PLLENABLE
SSTL-2 Class II
v
SSTL-3 Class I
v
SSTL-3 Class II
v
AGP (1× and 2× )
CTT
v
Table 2–23 shows the performance on each of the fast PLL clock inputs
when using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology.
Table 2–23. LVDS Performance on Fast PLL Input
Fast PLL Clock Input
Maximum Input Frequency (MHz)
CLK0, CLK2, CLK9, CLK11,
FPLL7CLK, FPLL8CLK, FPLL9CLK,
FPLL10CLK
717(1)
CLK1, CLK3, CLK8, CLK10
645
Note to Table 2–23:
(1) See the chapter DC & Switching Characteristics of the Stratix Device Handbook,
Volume 1 for more information.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for source-
synchronous transmitters or for general-purpose external clocks. There
are no dedicated external clock output pins. Any I/O pin can be driven
by the fast PLL global or regional outputs as an external output pin. The
I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank.
Phase Shifting
Stratix device fast PLLs have advanced clock shift capability that enables
programmable phase shifts. You can enter a phase shift (in degrees or
time units) for each PLL clock output port or for all outputs together in
one shift. You can perform phase shifting in time units with a resolution
range of 125 to 416.66 ps. This resolution is a function of the VCO period,
with the finest step being equal to an eighth (×0.125) of the VCO period.
Altera Corporation
July 2005
2–103
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
