PLLs & Clock Networks
External Clock Inputs
Each fast PLL supports single-ended or differential inputs for source
synchronous transmitters or for general-purpose use. Source-
synchronous receivers support differential clock inputs. The fast PLL
inputs are fed by CLK[0..3], CLK[8..11], and FPLL[7..10]CLK
pins, as shown in Figure 2–50 on page 2–85.
Table 2–22 shows the I/O standards supported by fast PLL input pins.
Table 2–22. Fast PLL Port I/O Standards (Part 1 of 2)
Input
I/O Standard
INCLK
v
PLLENABLE
LVTTL
v
v
LVCMOS
v
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
v
v
v
v
v
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
v
v
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
v
v
v
2–102
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
