Stratix Architecture
Figure 2–58. Stratix Device Fast PLL
Post-Scale
Counters
diffioclk1 (2)
Global or
÷l0
regional clock
txload_en (3)
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
rxload_en (3)
÷l1
Global or
regional clock
Global or
regional clock (1)
diffioclk2 (2)
8
Charge
Pump
Loop
Filter
Global or
regional clock
÷g0
PFD
VCO
Clock
Input
÷m
Notes to Figure 2–58:
(1) The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3) This signal is a high-speed differential I/O support SERDES control signal.
Clock Multiplication & Division
Stratix device fast PLLs provide clock synthesis for PLL output ports
using m/(post scaler) scaling factors. The input clock is multiplied by the
m feedback factor. Each output port has a unique post scale counter to
divide down the high-frequency VCO. There is one multiply divider, m,
per fast PLL with a range of 1 to 32. There are two post scale L dividers
for regional and/or LVDS interface clocks, and g0 counter for global clock
output port; all range from 1 to 32.
In the case of a high-speed differential interface, set the output counter to
1 to allow the high-speed VCO frequency to drive the SERDES. When
used for clocking the SERDES, the m counter can range from 1 to 30. The
VCO frequency is equal to fIN×m, where VCO frequency must be between
300 and 1000 MHz.
Altera Corporation
July 2005
2–101
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
