Stratix Architecture
The pllenablepin is a dedicated pin that enables/disables PLLs. When
the pllenablepin is low, the clock output ports are driven by GNDand
all the PLLs go out of lock. When the pllenablepin goes high again, the
PLLs relock and resynchronize to the input clocks. You can choose which
PLLs are controlled by the pllenablesignal by connecting the
pllenableinput port of the altpllmegafunction to the common
pllenableinput pin.
The aresetsignals are reset/resynchronization inputs for each PLL. The
aresetsignal should be asserted every time the PLL loses lock to
guarantee correct phase relationship between the PLL output clocks.
Users should include the aresetsignal in designs if any of the following
conditions are true:
■
■
PLL Reconfiguration or Clock switchover enables in the design.
Phase relationships between output clocks need to be maintained
after a loss of lock condition
The device input pins or logic elements (LEs) can drive these input
signals. When driven high, the PLL counters will reset, clearing the PLL
output and placing the PLL out of lock. The VCO will set back to its
nominal setting (~700 MHz). When driven low again, the PLL will
resynchronize to its input as it relocks. If the target VCO frequency is
below this nominal frequency, then the output frequency will start at a
higher value than desired as the PLL locks. If the system cannot tolerate
this, the clkenasignal can disable the output clocks until the PLL locks.
The pfdenasignals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term
drift to a lower frequency. The system continues running when the PLL
goes out of lock or the input clock is disabled. By maintaining the last
locked frequency, the system has time to store its current settings before
shutting down. You can either use your own control signal or a clkloss
status signal to trigger pfdena.
The clkenasignals control the enhanced PLL regional and global
outputs. Each regional and global output port has its own clkenasignal.
The clkenasignals synchronously disable or enable the clock at the PLL
output port by gating the outputs of the g and l counters. The clkena
signals are registered on the falling edge of the counter output clock to
enable or disable the clock without glitches. Figure 2–57 shows the
waveform example for a PLL clock port enable. The PLL can remain
locked independent of the clkenasignals since the loop-related counters
are not affected. This feature is useful for applications that require a low
power or sleep mode. Upon re-enabling, the PLL does not need a
Altera Corporation
July 2005
2–99
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
