Stratix Architecture
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
Input
FBIN
Output
I/O Standard
INCLK
v
PLLENABLE
EXTCLK
v
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
AGP (1× and 2× )
CTT
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure 2–56). These outputs do not have their own VCCand GNDsignals.
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
Figure 2–56. External Clock Outputs for Enhanced PLLs 11 & 12
g0
Counter
CLK13n, I/O, PLL11_OUT
or CLK6n, I/O, PLL12_OUT (1)
From Internal
Logic or IOE
Note to Figure 2–56:
(1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix devices can drive any enhanced PLL driven through the global
clock or regional clock network to any general I/O pin as an external
output clock. The jitter on the output clock is not guaranteed for these
cases.
Altera Corporation
July 2005
2–95
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
