PLLs & Clock Networks
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
pair of output pins (four pins total) has dedicated VCCand GNDpins to
reduce the output clock’s overall jitter by providing improved isolation
from switching I/O pins.
For PLLs 5 and 6, each pin of a single-ended output pair can either be in
phase or 180° out of phase. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as
well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology,
differential HSTL, and differential SSTL. Table 2–20 shows which I/O
standards the enhanced PLL clock pins support. When in single-ended or
differential mode, the two outputs operate off the same power supply.
Both outputs use the same standards in single-ended mode to maintain
performance. You can also use the external clock output pins as user
output pins if external enhanced PLL clocking is not needed.
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
Input
FBIN
Output
I/O Standard
INCLK
v
PLLENABLE
EXTCLK
v
LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
v
LVCMOS
v
v
2.5 V
v
v
1.8 V
v
v
1.5 V
v
v
3.3-V PCI
v
v
3.3-V PCI-X 1.0
LVPECL
v
v
v
v
3.3-V PCML
LVDS
v
v
v
v
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V GTL+
1.5-V HSTL Class I
v
v
2–94
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
