Stratix Architecture
Figure 2–55. External Clock Outputs for PLLs 5 & 6
From IOE (1), (2)
pll_out0p (3), (4)
(3)
e0 Counter
pll_out0n (3), (4)
pll_out1p (3), (4)
From IOE (1)
From IOE (1)
e1 Counter
pll_out1n (3), (4)
pll_out2p (3), (4)
From IOE (1)
4
From IOE (1)
e2 Counter
pll_out2n (3), (4)
pll_out3p (3), (4)
From IOE (1)
From IOE (1)
e3 Counter
pll_out3n (3), (4)
From IOE (1)
Notes to Figure 2–55:
(1) The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with IOE outputs.
(2) Two single-ended outputs are possible per output counter⎯either two outputs of the same frequency and phase or
one shifted 180°.
(3) EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two
pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n).
(4) Differential SSTL and HSTL outputs are implemented using two single-ended output buffers, which are
programmed to have opposite polarity.
Altera Corporation
July 2005
2–93
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
