PLLs & Clock Networks
During switchover, the PLL VCO continues to run and will either slow
down or speed up, generating frequency drift on the PLL outputs. The
clock switchover transitions without any glitches. After the switch, there
is a finite resynchronization period to lock onto new clock as the VCO
ramps up. The exact amount of time it takes for the PLL to relock relates
to the PLL configuration and may be adjusted by using the
programmable bandwidth feature of the PLL. The specification for the
maximum time to relock is 100 µs.
f
For more information on clock switchover, see AN 313, Implementing
Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change Stratix
device enhanced PLL counters and delay elements without reloading a
Programmer Object File (.pof). This provides considerable flexibility for
frequency synthesis, allowing real-time PLL frequency and output clock
delay variation. You can sweep the PLL output frequencies and clock
delay in prototype environments. The PLL reconfiguration feature can
also dynamically or intelligently control system clock speeds or tCO
delays in end systems.
Clock delay elements at each PLL output port implement variable delay.
Figure 2–54 shows a diagram of the overall dynamic PLL control feature
for the counters and the clock delay elements. The configuration time is
less than 20 μs for the enhanced PLL using a input shift clock rate of
22 MHz. The charge pump, loop filter components, and phase shifting
using VCO phase taps cannot be dynamically adjusted.
2–90
Altera Corporation
Stratix Device Handbook, Volume 1
July 2005
ALTERA [ ALTERA CORPORATION ]
