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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
Figure 2–53. Clock Switchover Circuitry  
CLK0_BAD  
CLK1_BAD  
Active Clock  
SMCLKSW  
Clock  
Sense  
Switch-Over  
State Machine  
CLKLOSS  
CLKSWITCH  
Δt  
INCLK0  
INCLK1  
MUXOUT  
PFD  
n Counter  
FBCLK  
Enhanced PLL  
There are two possible ways to use the clock switchover feature.  
Use automatic switchover circuitry for switching between inputs of  
the same frequency. For example, in applications that require a  
redundant clock with the same frequency as the primary clock, the  
switchover state machine generates a signal that controls the  
multiplexer select input on the bottom of Figure 2–53. In this case, the  
secondary clock becomes the reference clock for the PLL.  
Use the clkswitchinput for user- or system-controlled switch  
conditions. This is possible for same-frequency switchover or to  
switch between inputs of different frequencies. For example, if  
inclk0is 66 MHz and inclk1is 100 MHz, you must control the  
switchover because the automatic clock-sense circuitry cannot  
monitor primary and secondary clock frequencies with a frequency  
difference of more than 20%. This feature is useful when clock  
sources can originate from multiple cards on the backplane,  
requiring a system-controlled switchover between frequencies of  
operation. You can use clkswitchtogether with the lock signal to  
trigger the switch from a clock that is running but becomes unstable  
and cannot be locked onto.  
Altera Corporation  
July 2005  
2–89  
Stratix Device Handbook, Volume 1  
 
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