PLLs & Clock Networks
Figure 2–51. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs Note (1)
(1)
PLL5_OUT[3..0] CLK14
(2)
CLK12
(1)
PLL5_FB
CLK15
(2)
CLK13
E[0..3]
PLL 5
PLL 11
L0 L1 G0 G1 G2 G3
G0 G1 G2 G3 L0 L1
PLL11_OUT
RCLK10
RCLK11
Regional
Clocks
RCLK2
RCLK3
G12
G13
G14
G15
Global
Clocks
G4
G5
G6
G7
RCLK6
RCLK7
Regional
Clocks
RCLK12
RCLK13
PLL12_OUT
L0 L1 G0 G1 G2 G3
PLL 6
G0 G1 G2 G3 L0 L1
PLL 12
PLL6_OUT[3..0]
PLL6_FB
(1)
CLK6 (1)
CLK7 (2)
CLK4
CLK5
(2)
Notes to Figure 2–51:
(1) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs.
(2) CLK4, CLK6, CLK12, and CLK14feed the corresponding PLL’s inclk0port.
(3) CLK5, CLK7, CLK13, and CLK15feed the corresponding PLL’s inclk1port.
(4) The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12.
2–86
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
