ACEX 1K Programmable Logic Device Family Data Sheet
Table 43. EP1K30 External Bidirectional Timing Parameters
Notes (1), (2)
Symbol
Speed Grade
-2
Unit
-1
-3
Min
Max
Min
Max
Min
Max
tINSUBIDIR (3)
tINHBIDIR (3)
tINSUBIDIR (4)
2.8
0.0
3.8
0.0
2.0
3.9
0.0
4.9
0.0
2.0
5.2
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
INHBIDIR (4)
tOUTCOBIDIR (3)
tXZBIDIR (3)
–
4.9
6.1
6.1
3.9
5.1
5.1
5.9
7.5
7.5
4.9
6.5
6.5
2.0
7.6
9.7
9.7
–
tZXBIDIR (3)
t
OUTCOBIDIR (4)
tXZBIDIR (4)
ZXBIDIR (4)
0.5
0.5
–
–
t
–
Notes to tables:
(1) All timing parameters are described in Tables 22 through 29 in this data sheet.
(2) These parameters are specified by characterization.
(3) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(4) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 44 through 50 show EP1K50 device external timing parameters.
Table 44. EP1K50 Device LE Timing Microparameters (Part 1 of 2)
Note (1)
Symbol
Speed Grade
-2
Unit
-1
-3
Min
Max
Min
Max
Min
Max
tLUT
0.6
0.5
0.6
0.2
0.6
0.1
0.4
0.1
0.5
0.5
0.8
0.6
0.7
0.3
0.7
0.1
0.5
0.1
0.8
0.6
1.1
0.8
0.9
0.4
0.9
0.1
0.6
0.1
1.0
0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLUT
tRLUT
tPACKED
tEN
tCICO
tCGEN
tCGENR
tCASC
tC
70
Altera Corporation