Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
1–15
Functional Description
Figure 1–4 shows an FPP configuration schematic with the external flash interface in
use.
Figure 1–4. FPP Configuration with External Flash Interface (Note 1)
Enhanced Configuration
Device
V
PLD or Processor
V
CC
CC
Stratix Series
or
APEX II Device
WE#C
RP#C
DCLK
DATA[7..0]
OE
WE#
RP#
WE#F
RP#F
DCLK
n
A[20..0]
RY/BY#
CE#
A[20..0] (2)
RY/BY# (5)
CE#
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
MSEL
nCEO
nCS
nINIT_CONF
OE#
OE#
N.C.
DQ[15..0]
DQ[15..0]
nCE
V
CC
V (6)
CC
WP#
BYTE# (3)
VCCW
GND
TM1
PORSEL
(4)
(4)
PGM[2..0]
TMO
EXCLK
(4)
GND
C-A0 (3)
C-A1 (3)
C-A15 (3)
C-A16 (3)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 1–4:
(1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.
(2) Pin A20in EPC16 devices, pins A20and A19in EPC8 devices, and pins A20, A19, and A18in EPC4 devices should be left floating. These pins
should not be connected to any signal; they are no-connect pins.
(3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15to F-A15, C-A16to
F-A16, and BYTE#to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:
C-RP#to F-RP#, C-WE#to F-WE#, TM1to VCC, TM0to GND, and WP#to VCC
(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 1–10.
(5) RY/BY#pin is only available for Sharp flash-based EPC8 and EPC16.
.
(6) To protect Intel Flash based EPC devices content, isolate the VCCW supply from VCC. For more information, refer section “Intel-Flash-Based EPC
Device Protection” on page 1–15.
Intel-Flash-Based EPC Device Protection
In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices
with Intel flash, Altera recommends four methods to protect the Intel Flash content in
EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash.
The methods are listed here in the order of descending protection level:
1. Using an RP#of less than 0.3 V on power-up and power-down for a minimum of
100 ns to a maximum 25 ms disables all control pins, making it impossible for a
write to occur.
© December 2009 Altera Corporation
Configuration Handbook (Complete Two-Volume Set)
ALTERA [ ALTERA CORPORATION ]
