1. Introduction
C51001-1.5
Introduction
The Cyclone
®
field programmable gate array family is based on a 1.5-V,
0.13-μm, all-layer copper SRAM process, with densities up to
20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like
phase-locked loops (PLLs) for clocking and a dedicated double data rate
(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)
memory requirements, Cyclone devices are a cost-effective solution for
data-path applications. Cyclone devices support various I/O standards,
including LVDS at data rates up to 640 megabits per second (Mbps), and
66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),
for interfacing with and supporting ASSP and ASIC devices. Altera also
offers new low-cost serial configuration devices to configure Cyclone
devices.
The Cyclone device family offers the following features:
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Features
2,910 to 20,060 LEs, see
Table 1–1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66- and 33-MHz, 64- and 32-bit PCI standard
High-speed (640 Mbps) LVDS I/O support
Low-speed (311 Mbps) LVDS I/O support
311-Mbps RSDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera
®
MegaCore
®
functions and Altera Megafunctions Partners
Program (AMPP
SM
) megafunctions.
Table 1–1. Cyclone Device Features (Part 1 of 2)
Feature
LEs
M4K RAM blocks (128
×
36 bits)
EP1C3
2,910
13
EP1C4
4,000
17
EP1C6
5,980
20
EP1C12
12,060
52
EP1C20
20,060
64
Altera Corporation
May 2008
1–1
Preliminary
ALTERA [ ALTERA CORPORATION ]
