Cyclone FPGA Family Data Sheet
Preliminary Information
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Table 39. Cyclone Device Timing Model Status
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Preliminary
Final
v
v
v
v
v
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 40 through 43 describe the Cyclone
device internal timing microparameters for LEs, IOEs, M4K memory
structures, and MultiTrack interconnects.
Table 40. LE Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
tH
tCO
tLUT
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
74
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