Preliminary Information
Cyclone FPGA Family Data Sheet
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 44 through 47 show the internal
timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP
blocks, and MultiTrack interconnects.
Table 44. LE Internal Timing Microparameters
Symbol
-6
-7
-8
Unit
Min
Max
Min
Max
Min
Max
tSU
29
12
33
13
37
15
ps
ps
ps
ps
ps
ps
ps
tH
tCO
tLUT
tCLR
tPRE
173
454
198
522
224
590
129
129
107
148
148
123
167
167
139
tCLKHL
Table 45. IOE Internal Timing Microparameters
Symbol -6 -7
-8
Unit
Min
Max
Min
Max
Min
Max
tSU
tH
98
65
107
71
117
78
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tCO
161
177
193
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
1,107
1,112
2,776
2,764
1,217
1,223
3,053
3,040
1,328
1,334
3,331
3,316
280
280
95
308
308
104
336
336
114
tPRE
tCLKHL
Altera Corporation
77
ALTERA [ ALTERA CORPORATION ]
