Preliminary Information
Cyclone FPGA Family Data Sheet
Tables 49 through 50 show the external timing parameters on column and
row pins for EP1C3 devices.
Table 49. EP1C3 Column Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.496
0.000
2.000
2.715
0.000
2.000
2.935
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.656
5.283
5.283
4.049
5.840
5.840
4.445
6.398
6.398
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.195
0.000
0.500
3.527
3.527
1.308
0.000
0.500
3.885
3.885
1.421
0.000
0.500
4.244
4.244
1.900
2.094
2.291
Table 50. EP1C3 Row Pin Global Clock External I/O Timing Parameters
Symbol -6 Speed Grade -7 Speed Grade -8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.574
0.000
2.000
2.806
0.000
2.000
3.041
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.561
5.147
5.147
3.939
5.684
5.684
4.319
6.223
6.223
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.273
0.000
0.500
3.391
3.391
1.399
0.000
0.500
3.729
3.729
1.527
0.000
0.500
4.069
4.069
1.805
1.984
2.165
Altera Corporation
81
ALTERA [ ALTERA CORPORATION ]
