Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 36 shows the timing requirements for the JTAG signals.
Figure 36. Cyclone JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 21 shows the JTAG timing parameters and values for Cyclone
devices.
Table 21. Cyclone JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
tJCP
TCKclock period
TCKclock high time
TCKclock low time
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
tJCL
50
tJPSU
tJPH
JTAG port setup time
20
JTAG port hold time
45
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
35
35
35
64
Altera Corporation
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