Cyclone
FPGA Family
®
March 2003, ver. 1.1
Data Sheet
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
Introduction
Preliminary
Information
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2,910 to 20,060 LEs, see Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Features...
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Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
Altera MegaCore functions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Table 1. Cyclone Device Features
Feature
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
LEs
2,910
13
4,000
17
5,980
20
12,060
52
20,060
64
M4K RAM blocks (128 × 36 bits)
Total RAM bits
59,904
1
78,336
2
92,160
2
239,616
2
294,912
2
PLLs
Maximum user I/O pins (1)
104
301
185
249
301
Note to Table 1:
(1) This parameter includes global clock pins.
Altera Corporation
1
DS-CYCLONE-1.1
ALTERA [ ALTERA CORPORATION ]
