Cyclone FPGA Family Data Sheet
Preliminary Information
Table 18. Cyclone JTAG Instructions
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
EXTEST(1)
BYPASS
00 0000 0000
11 1111 1111
00 0000 0111
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE
Selects the 32-bit USERCODE register and places it between the
TDIand TDOpins, allowing the USERCODE to be serially shifted
out of TDO.
IDCODE
00 0000 0110
00 0000 1011
Selects the IDCODE register and places it between TDIand TDO,
allowing the IDCODE to be serially shifted out of TDO.
HIGHZ(1)
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
CLAMP(1)
00 0000 1010
Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR instructions
Used when configuring a Cyclone device via the JTAG port with a
MasterBlasterTM or ByteBlasterMVTM download cable, or when
using a Jam File or Jam Byte-Code File via an embedded
processor.
PULSE_NCONFIG
CONFIG_IO
00 0000 0001
00 0000 1101
Emulates pulsing the nCONFIGpin low to trigger reconfiguration
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
Once issued, the CONFIG_IOinstruction will hold nSTATUSlow to
reset the configuration device. nSTATUSis held low until the device
is reconfigured.
SignalTap II
instructions
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Note to Table 18:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
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