Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 34 illustrates DDR SDRAM and FCRAM interfacing from the I/O
through the dedicated circuitry to the logic array.
Figure 34. DDR SDRAM & FCRAM Interfacing
DQS
OE LE
Register
OE
DQ
OE
OE LE
Output LE
Register
Register
OE LE
Register
V
CC
Output LE
Registers
t
∆
clk
Adjacent
LAB LEs
OE LE
Register
Input LE
Registers
DataA
DataB
Output LE
Register
-90˚ clk
GND
Output LE
Registers
Input LE
Registers
Programmable
Delay Chain
PLL
Global Clock
Phase Shifted -90˚
LE
Register
LE
Register
Resynchronizing
Global Clock
Adjacent LAB LEs
54
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