Preliminary Information
Cyclone FPGA Family Data Sheet
LVDS I/O Pins
A subset of pins in all four I/O banks supports LVDS interfacing. These
dual-purpose LVDS pins require an external-resistor network at the
transmitter channels in addition to 100-Ω termination resistors on receiver
channels. These pins do not contain dedicated serialization or
deserialization circuitry; therefore, internal logic performs serialization
and deserialization functions.
Table 16 shows the total number of supported LVDS channels per device
density.
Table 16. Cyclone Device LVDS Channels
Device
Pin Count
Number of LVDS Channels
EP1C3
EP1C4
EP1C6
100
144
324
400
144
240
256
240
256
324
324
400
(1)
34
103
129
29
72
72
EP1C12
EP1C20
66
72
103
95
129
Note to Table 16:
(1) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O
standard.
MultiVolt I/O Interface
The Cyclone architecture supports the MultiVolt I/O interface feature,
which allows Cyclone devices in all packages to interface with systems of
different supply voltages. The devices have one set of VCC pins for
internal operation and input buffers (VCCINT), and four sets for I/O
output drivers (VCCIO).
Altera Corporation
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