I/O Structure
Figure 2–28. Row I/O Block Connection to the Interconnect
R4 Interconnects
C4 Interconnects
I/O Block Local
Interconnect
21 Data and
Control Signals
from Logic Array (1)
21
LAB
Row
I/O Block
io_datain[2..0] and
comb_io_datain[2..0] (2)
Direct Link
Interconnect
from Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
Row I/O Block
Contains up to
Three IOEs
io_clk[5:0]
LAB Local
Interconnect
Notes to Figure 2–28:
(1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
(2) Each of the three IOEs in the row I/O block can have one io_dataininput (combinatorial or registered) and one
comb_io_datain(combinatorial) input.
Altera Corporation
January 2007
2–41
Preliminary
ALTERA [ ALTERA CORPORATION ]
