Embedded Memory
Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode
Notes (1), (2)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
data[ ]
address[ ]
byteena[ ]
D
ENA
Q
Q
Q
Data In
Read Address
D
ENA
To MultiTrack
Interconnect
Data Out
D
Q
ENA
Byte Enable
D
ENA
wraddress[ ]
Write Address
D
ENA
Q
Q
rden
Read Enable
D
ENA
wren
outclken
Write
Pulse
Generator
D
ENA
Q
Write Enable
inclken
inclock
outclock
Notes to Figure 2–19:
(1) All registers shown except the rden register have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Altera Corporation
January 2007
2–27
Preliminary
ALTERA [ ALTERA CORPORATION ]
