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EP1C12Q240I7ES 参数 Datasheet PDF下载

EP1C12Q240I7ES图片预览
型号: EP1C12Q240I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Logic Elements  
Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full  
adder. One portion of the LUT generates the sum of two bits using the  
input signals and the appropriate carry-in bit; the sum is routed to the  
output of the LE. The register can be bypassed for simple adders or used  
for accumulator functions. Another portion of the LUT generates carry-  
out bits. An LAB-wide carry-in bit selects which chain is used for the  
addition of given inputs. The carry-in signal for each chain, carry-in0  
or carry-in1, selects the carry-out to carry forward to the carry-in  
signal of the next-higher-order bit. The final carry-out signal is routed to  
an LE, where it is fed to local, row, or column interconnects.  
Figure 2–8. Carry Select Chain  
LAB Carry-In  
0
1
LAB Carry-In  
Sum1  
A1  
B1  
LE1  
LE2  
LE3  
LE4  
LE5  
Carry-In0  
Carry-In1  
Sum2  
Sum3  
Sum4  
Sum5  
A2  
B2  
LUT  
LUT  
data1  
data2  
Sum  
A3  
B3  
A4  
B4  
LUT  
LUT  
A5  
B5  
0
1
Carry-Out0  
Carry-Out1  
Sum6  
Sum7  
Sum8  
Sum9  
Sum10  
A6  
B6  
LE6  
LE7  
LE8  
LE9  
A7  
B7  
A8  
B8  
A9  
B9  
A10  
B10  
LE10  
LAB Carry-Out  
Altera Corporation  
January 2007  
2–11  
Preliminary