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EP1C12F324I7ES 参数 Datasheet PDF下载

EP1C12F324I7ES图片预览
型号: EP1C12F324I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Timing Model  
Typically, the user-mode current during device operation is lower than  
the power-up current in Table 4–17. Altera recommends using the  
Cyclone Power Calculator, available on the Altera web site, to estimate  
the user-mode ICCINT consumption and then select power supplies or  
regulators based on the higher value.  
The DirectDrive technology and MultiTrack interconnect ensure  
predictable performance, accurate simulation, and accurate timing  
analysis across all Cyclone device densities and speed grades. This  
section describes and specifies the performance, internal, external, and  
PLL timing specifications.  
Timing Model  
All specifications are representative of worst-case supply voltage and  
junction temperature conditions.  
Preliminary & Final Timing  
Timing models can have either preliminary or final status. The  
Quartus® II software issues an informational message during the design  
compilation if the timing models are preliminary. Table 4–18 shows the  
status of the Cyclone device timing models.  
Preliminary status means the timing model is subject to change. Initially,  
timing numbers are created using simulation results, process data, and  
other known parameters. These tests are used to make the preliminary  
numbers as close to the actual timing parameters as possible.  
Final timing numbers are based on actual device operation and testing.  
These numbers reflect the actual performance of the device under  
worst-case voltage and junction temperature conditions.  
Table 4–18. Cyclone Device Timing Model Status  
Device  
EP1C3  
EP1C4  
EP1C6  
EP1C12  
EP1C20  
Preliminary  
Final  
v
v
v
v
v
Altera Corporation  
January 2007  
4–9  
Preliminary