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EP1C12F256C8N 参数 Datasheet PDF下载

EP1C12F256C8N图片预览
型号: EP1C12F256C8N
PDF下载: 下载PDF文件 查看货源
内容描述: 第一节的Cyclone FPGA系列数据手册 [Section I. Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 106 页 / 1386 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
preset/load, synchronous clear, synchronous load, and clock enable  
control for the register. These LAB-wide signals are available in all LE  
modes. The addnsubcontrol signal is allowed in arithmetic mode.  
The Quartus II software, in conjunction with parameterized functions  
such as library of parameterized modules (LPM) functions, automatically  
chooses the appropriate mode for common functions such as counters,  
adders, subtractors, and arithmetic functions. If required, you can also  
create special-purpose functions that specify which LE operating mode to  
use for optimal performance.  
Normal Mode  
The normal mode is suitable for general logic applications and  
combinatorial functions. In normal mode, four data inputs from the LAB  
local interconnect are inputs to a four-input LUT (see Figure 2–6). The  
Quartus II Compiler automatically selects the carry-in or the data3  
signal as one of the inputs to the LUT. Each LE can use LUT chain  
connections to drive its combinatorial output directly to the next LE in the  
LAB. Asynchronous load data for the register comes from the data3  
input of the LE. LEs in normal mode support packed registers.  
Figure 2–6. LE in Normal Mode  
sload  
sclear  
aload  
(LAB Wide) (LAB Wide)  
(LAB Wide)  
Register chain  
connection  
addnsub (LAB Wide)  
ALD/PRE  
(1)  
Row, column, and  
direct link routing  
ADATA  
D
Q
data1  
data2  
Row, column, and  
direct link routing  
ENA  
CLRN  
data3  
cin (from cout  
of previous LE)  
4-Input  
LUT  
clock (LAB Wide)  
Local routing  
data4  
ena (LAB Wide)  
aclr (LAB Wide)  
LUT chain  
connection  
Register  
chain output  
Register Feedback  
Note to Figure 2–6:  
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.  
2–8  
Preliminary  
Altera Corporation  
May 2008