Chapter 2: Arria GX Architecture
Transceivers
2–3
Each transceiver channel is full-duplex and consists of a transmitter channel and a
receiver channel.
The transmitter channel contains the following sub-blocks:
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■
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■
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
The receiver channel contains the following:
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Receiver differential input buffer
Receiver lock detector and run length checker
CRU
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Receiver phase compensation FIFO buffer
You can configure the transceiver channels to the desired functional modes using the
ALT2GXB MegaCore instance in the Quartus
®
II MegaWizard
™
Plug-in Manager for
the Arria GX device family. Depending on the selected functional mode, the
Quartus II software automatically configures the transceiver channels to employ a
subset of the sub-blocks listed above.
Transmitter Path
This section describes the data path through the Arria GX transmitter. The sub-blocks
are described in order from the PLD-transmitter parallel interface to the serial
transmitter buffer.
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a reference
clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a
low-speed parallel clock to clock the transmitter digital logic (PCS).
The CMU is further divided into three sub-blocks:
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■
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One transmitter PLL
One central clock divider block
Four local clock divider blocks (one per channel)
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
