4–32
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2)
I/O Standard
Capacitive Load
Units
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
1.8 V
1.5 V
PCI
0
0
10
10
0
PCI-X
SSTL-2 Class I
SSTL-2 Class II
0
SSTL-18 Class I
0
SSTL-18 Class II
0
1.5-V HSTL Class I
0
1.5-V HSTL Class II
0
1.8-V HSTL Class I
0
1.8-V HSTL Class II
0
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
0
0
0
0
0
0
0
0
0
Typical Design Performance
The following section describes the typical design performance for the Arria GX
device family.
User I/O Pin Timing
Table 4–48 through Table 4–77 show user I/O pin timing for Arria GX devices. I/O
buffer tSU, tH, and tCO are reported for the cases when I/O clock is driven by a
non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For tSU, tH,
and tCO using regional clock, add the value from the adder tables listed for each device
to the GCLK/GCLK-PLLvalues for the device.
EP1AGX20 I/O Timing Parameters
Table 4–48 through Table 4–51 show the maximum I/O timing parameters for
EP1AGX20 devices for I/O standards which support general purpose I/O pins.
Table 4–48 describes the row pin delay adders when using the regional clock in
Arria GX devices.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
