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EP1AGX 参数 Datasheet PDF下载

EP1AGX图片预览
型号: EP1AGX
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内容描述: 第一节的Arria GX器件数据手册 [Section I. Arria GX Device Data Sheet]
分类和应用:
文件页数/大小: 234 页 / 3509 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 4: DC and Switching Characteristics  
4–25  
Power Consumption  
Table 4–41. Series On-Chip Termination Specification for Left I/O Banks  
Resistance Tolerance  
Symbol  
Description  
Conditions  
Commercial  
Industrial  
Max  
Units  
Max  
25-RS 3.3/2.5 Internal series termination without  
calibration (25-setting  
VCCIO = 3.3/2.5V  
VCCIO = 3.3/2.5/1.8V  
VCCIO = 1.5V  
30  
30  
30  
36  
25  
%
%
%
%
50-RS  
3.3/2.5/1.8  
Internal series termination without  
calibration (50-setting  
30  
36  
20  
50-RS 1.5  
Internal series termination without  
calibration (50-setting  
RD  
Internal differential termination for  
VCCIO = 2.5V  
LVDS (100-setting)  
Pin Capacitance  
Table 4–42 shows the Arria GX device family pin capacitance.  
Table 4–42. Arria GX Device Capacitance (Note 1)  
Symbol  
Parameter  
Typical  
Units  
pF  
CIOTB  
CIOL  
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.  
5.0  
6.1  
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed differential  
receiver and transmitter pins.  
pF  
CCLKTB  
CCLKL  
Input capacitance on top/bottom clock input pins: CLK[4..7]and CLK[12..15].  
Input capacitance on left clock inputs: CLK0and CLK2.  
6.0  
6.1  
3.3  
6.7  
pF  
pF  
pF  
pF  
CCLKL+  
COUTFB  
Input capacitance on left clock inputs: CLK1and CLK3.  
Input capacitance on dual-purpose clock output/feedback pins in PLL banks 11 and 12.  
Note to Table 4–42:  
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF.  
Power Consumption  
Altera offers two ways to calculate power for a design: the Excel-based PowerPlay  
early power estimator power calculator and the Quartus II PowerPlay power analyzer  
feature.  
The interactive Excel-based PowerPlay Early Power Estimator is typically used prior  
to designing the FPGA in order to get an estimate of device power. The Quartus II  
PowerPlay Power Analyzer provides better quality estimates based on the specifics of  
the design after place-and-route is complete. The power analyzer can apply a  
combination of user-entered, simulation-derived and estimated signal activities  
which, combined with detailed circuit models, can yield very accurate power  
estimates.  
In both cases, these calculations should only be used as an estimation of power, not as  
a specification.  
© December 2009 Altera Corporation  
Arria GX Device Handbook, Volume 1