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EP1AGX 参数 Datasheet PDF下载

EP1AGX图片预览
型号: EP1AGX
PDF下载: 下载PDF文件 查看货源
内容描述: 第一节的Arria GX器件数据手册 [Section I. Arria GX Device Data Sheet]
分类和应用:
文件页数/大小: 234 页 / 3509 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3–8  
Chapter 3: Configuration and Testing  
Automated Single Event Upset (SEU) Detection  
f
For more information about Arria GX PLLs, refer to the PLLs in Arria GX Devices  
chapter.  
Automated Single Event Upset (SEU) Detection  
Arria GX devices offer on-chip circuitry for automated checking of single event upset  
(SEU) detection. Some applications that require the device to operate error free at high  
elevations or in close proximity to Earth’s North or South Pole requires periodic  
checks to ensure continued data integrity. The error detection cyclic redundancy  
check (CRC) feature controlled by the Device and Pin Options dialog box in the  
Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of  
the best options for mitigating SEU.  
You can implement the error detection CRC feature with existing circuitry in Arria GX  
devices, eliminating the need for external logic. Arria GX devices compute CRC  
during configuration. The Arria GX device checks the computed-CRC against an  
automatically computed CRC during normal operation. The CRC_ERRORpin reports  
a soft error when configuration SRAM data is corrupted, triggering device  
reconfiguration.  
Custom-Built Circuitry  
Dedicated circuitry is built into Arria GX devices to automatically perform error  
detection. This circuitry constantly checks for errors in the configuration SRAM cells  
while the device is in user mode. You can monitor one external pin for the error and  
use it to trigger a reconfiguration cycle. You can select the desired time between  
checks by adjusting a built-in clock divider.  
Software Interface  
Beginning with version 7.1 of the Quartus II software, you can turn on the automated  
error detection CRC feature in the Device and Pin Options dialog box. This dialog  
box allows you to enable the feature and set the internal frequency of the CRC  
between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the  
internal configuration SRAM bits in the Arria GX FPGA.  
f
For more information about CRC, refer to AN 357: Error Detection Using CRC in Altera  
FPGAs.  
Arria GX Device Handbook, Volume 1  
© December 2009 Altera Corporation