2–4
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–3 shows the block diagram of the clock multiplier unit.
Figure 2–3. Clock Multiplier Unit
CMU Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider Block
Gen Block
Reference Clock
from REFCLKs,
Global Clock (1),
Inter-Transceiver
Lines
Central Clock
Divider
Transmitter
PLL
Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Local Clock
DTiviXderCBlloocckk
Gen Block
Transmitter Channels [1:0]
The transmitter PLL multiplies the input reference clock to generate the high-speed
serial clock required to support the intended protocol. It implements a half-rate
voltage controlled oscillator (VCO) that generates a clock at half the frequency of the
serial data rate for which it is configured.
Figure 2–4 shows the block diagram of the transmitter PLL.
Figure 2–4. Transmitter PLL
Transmitter PLL
/M(1)
To
Inter-Transceiver Lines
up
down
Dedicated
REFCLK0
/2
/2
Phase
Frequency
Detector
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
High Speed
Serial Clock
/L(1)
Dedicated
REFCLK1
INCLK
Inter-Transceiver Lines[2:0]
Global Clock (2)
Notes to Figure 2–4:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your
selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).
(2) The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
One of two available dedicated reference clock input pins (REFCLK0or REFCLK1)
of the associated transceiver block
■
PLD global clock network (must be driven directly from an input clock pin and
cannot be driven by user logic or enhanced PLL)
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
