Chapter 2: Arria GX Architecture
2–5
Transceivers
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Inter-transceiver block lines driven by reference clock input pins of other
transceiver blocks
1
Altera® recommends using the dedicated reference clock input pins (REFCLK0or
REFCLK1) to provide reference clock for the transmitter PLL.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter
Input reference frequency range
Data rate support
Specifications
50 MHz to 622.08 MHz
600 Mbps to 3.125 Gbps
Low, medium, or high
Bandwidth
The transmitter PLL output feeds the central clock divider block and the local clock
divider blocks. These clock divider blocks divide the high-speed serial clock to
generate the low-speed parallel clock for the transceiver PCS logic and
PLD-transceiver interface clock.
Transmitter Phase Compensation FIFO Buffer
A transmitter phase compensation FIFO is located at each transmitter channel’s logic
array interface. It compensates for the phase difference between the transmitter PCS
clock and the local PLD clock. The transmitter phase compensation FIFO is used in all
supported functional modes. The transmitter phase compensation FIFO buffer is eight
words deep in PCI Express (PIPE) mode and four words deep in all other modes.
f
For more information about architecture and clocking, refer to the Arria GX Transceiver
Architecture chapter.
Byte Serializer
The byte serializer takes in two-byte wide data from the transmitter phase
compensation FIFO buffer and serializes it into a one-byte wide data at twice the
speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows
clocking the PLD-transceiver interface at half the speed when compared with the
transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After
serialization, the byte serializer transmits the least significant byte (LSByte) first and
the most significant byte (MSByte) last.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
