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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Power Consumption  
Table 4–42. Arria GX Device Capacitance Note (1) (Part 2 of 2)  
Symbol  
Parameter  
Typical  
Unit  
COUTFB  
Input capacitance on dual-purpose clock output/feedback pins in PLL  
banks 11 and 12.  
6.7  
pF  
Note to Table 4–42:  
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement  
accuracy is within 0.5 pF.  
Altera offers two ways to calculate power for a design: the Excel-based  
PowerPlay early power estimator power calculator and the Quartus II  
PowerPlay power analyzer feature.  
Power  
Consumption  
The interactive Excel-based PowerPlay Early Power Estimator is typically  
used prior to designing the FPGA in order to get an estimate of device  
power. The Quartus II PowerPlay Power Analyzer provides better quality  
estimates based on the specifics of the design after place-and-route is  
complete. The power analyzer can apply a combination of user-entered,  
simulation-derived and estimated signal activities which, combined with  
detailed circuit models, can yield very accurate power estimates.  
In both cases, these calculations should only be used as an estimation of  
power, not as a specification.  
f
For more information on PowerPlay tools, refer to the PowerPlay Early  
Power Estimator and PowerPlay Power Analyzer paper and the PowerPlay  
Power Analysis chapter in volume 3 of the Quartus II Handbook.  
The PowerPlay early power estimator is available on the Altera web site  
at www.altera. com. See Table 4–14 on page 18 for typical ICC standby  
specifications.  
The DirectDrive technology and MultiTrack interconnect ensures  
predictable performance, accurate simulation, and accurate timing  
analysis across all Arria GX device densities and speed grades. This  
section describes and specifies the performance of I/Os.  
I/O Timing  
Model  
All specifications are representative of worst-case supply voltage and  
junction temperature conditions.  
1
The timing numbers listed in the tables of this section are  
extracted from the Quartus II software, version 7.1.  
4–34  
Altera Corporation  
May 2008  
Arria GX Device Handbook, Volume 1  
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