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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Bus Hold Specifications  
Table 4–39 shows the Arria GX device family bus hold specifications.  
Table 4–39. Bus Hold Parameters  
VCCIO Level  
1.8 V  
Parameter Conditions  
Unit  
μA  
1.2 V  
1.5 V  
2.5 V  
3.3 V  
Min Max Min Max Min Max Min  
Max Min Max  
Low  
V
IN > VIL  
22.5  
25  
30  
50  
70  
sustaining  
current  
(maximum)  
High  
V
IN < VIH  
–22.5  
–25  
–30  
–50  
–70  
μA  
sustaining  
current  
(minimum)  
Low  
overdrive  
current  
0 V < VIN  
VCCIO  
<
<
120  
160  
–160  
1.0  
200  
–200  
1.07  
300  
–300  
1.7  
500  
μA  
High  
overdrive  
current  
0 V < VIN  
VCCIO  
–120  
–500 μA  
Bus-hold  
trip point  
0.45 0.95 0.5  
0.68  
0.7  
0.8  
2.0  
V
On-Chip Termination Specifications  
Tables 4–40 and 4–41 define the specification for internal termination  
resistance tolerance when using series or differential on-chip termination.  
Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks (Part 1 of 2)  
Resistance Tolerance  
Symbol  
Description  
Conditions  
Commercial  
Max  
Industrial  
Max  
Unit  
25-Ω RS  
3.3/2.5  
Internal series termination without  
calibration (25-Ω setting)  
VCCIO = 3.3/2.5V  
VCCIO = 3.3/2.5V  
VCCIO = 1.8V  
30  
30  
30  
30  
30  
30  
30  
30  
%
50-Ω RS  
3.3/2.5  
Internal series termination without  
calibration (50-Ω setting)  
%
%
%
25-Ω RS  
1.8  
Internal series termination without  
calibration (25-Ω setting)  
50-Ω RS  
Internal series termination without  
VCCIO = 1.8V  
calibration (50-Ω setting)  
1.8  
4–32  
Altera Corporation  
May 2008  
Arria GX Device Handbook, Volume 1  
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