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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Operating Conditions  
Table 4–19. 1.5-V I/O Specifications  
Symbol  
VCCIO (1)  
VIH  
Parameter  
Output supply voltage  
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low-level output voltage  
Conditions  
Minimum  
1.425  
Maximum  
1.575  
Unit  
V
0.65 VCCIO  
–0.3  
VCCIO + 0.3  
0.35 VCCIO  
V
VIL  
V
VOH  
IOH = –2 mA (2)  
IOL = 2 mA (2)  
0.75 VCCIO  
V
VOL  
0.25 VCCIO  
V
Notes to Table 4–19:  
(1) The Arria GX device VCCIO voltage level support of 1.5 to 5% is narrower than defined in the normal range of the  
EIA/JEDEC standard.  
(2) This specification is supported across all the programmable drive settings available for this I/O standard as shown  
in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.  
Figures 4–5 and 4–6 show receiver input and transmitter output  
waveforms, respectively, for all differential I/O standards (LVDS and  
LVPECL).  
Figure 4–5. Receiver Input Waveforms for Differential I/O Standards  
Single-Ended Waveform  
Positive Channel (p) = V  
IH  
V
ID  
Negative Channel (n) = V  
IL  
V
CM  
Ground  
Differential Waveform  
V
ID  
p n = 0 V  
V
V
ID  
ID (Peak-to-Peak)  
4–22  
Arria GX Device Handbook, Volume 1  
Altera Corporation  
May 2008  
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