Features
Table 1–1. Arria GX Device Features (Part 2 of 2)
EP1AGX20C
Feature
C
Source-
synchronous
receive
channels
Source-
synchronous
transmit
channels
M512 RAM
blocks (32 ×
18 bits)
M4K RAM
blocks (128 ×
36 bits)
M-RAM
blocks (4096
× 144 bits)
Total RAM
bits
Embedded
multipliers
(18 × 18)
DSP blocks
PLLs
Maximum
user I/O pins
31
EP1AGX35C/D
C
31
EP1AGX50C/D
C
31
EP1AGX60C/D/E
C
31
EP1AGX90E
E
E
47
D
31
D
31, 42
D
31
42
29
29
29
29
29, 42
29
29
42
45
166
197
313
326
478
118
140
242
252
400
1
1
2
2
4
1,229,184
40
1,348,416
56
2,475,072
104
2,528,640
128
4,477,824
176
10
4
230, 341
230
14
4
341
4
229
26
4, 8
350, 514
229
4
32
8
350
514
44
8
538
Arria GX devices are available in space-saving FBGA packages (refer to
All Arria GX devices support vertical migration within the
same package. With vertical migration support, designers can migrate to
devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. For I/O pin migration
Altera Corporation
May 2008
1–3
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
