FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 13. Bidirectional I/O Registers
Row and Column
Interconnect
2 Dedicated
Clock Inputs
Peripheral
4 Dedicated
Control Bus
Inputs
2
OE Register
4
12
D
Q
ENA
VCC
CLRN
Chip-Wide
Reset
VCC
Chip-Wide
Output Enable
OE[7..0]
VCC
Output Register
D
Q
CLK[1..0]
CLK[3..2]
ENA
CLRN
Open-Drain
Output
VCC
ENA[5..0]
Slew-Rate
Control
VCC
CLRN[1..0]
Chip-Wide
Reset
Input Register
D
Q
VCC
ENA
CLRN
Chip-Wide
Reset
Altera Corporation
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