Stratix II EP2S60 DSP Development Board Data Sheet
Table 18. D/A B (U15, J17) Stratix II Pin-Outs
Signal Name
Stratix II Pin
dacB_D1 (MSB) (1)
dacB_D2
W4
W5
dacB_D3
Y6
dacB_D4
Y7
dacB_D5
Y8
dacB_D6
Y9
dacB_D7
Y10
Y11
AB5
AB6
AA10
AA11
AA6
AA7
dacB_D8
dacB_D9
dacB_D10
dacB_D11
dacB_D12
dacB_D13
dacB_D14 (LSB)
Note to Table 18:
(1) The Texas Instruments (TI) naming conventions differ from those of Altera
Corporation. The TI data sheet for the DAC 904 D/A converter lists bit 1 as the
most significant bit (MSB) and bit 14 as the least significant bit (LSB).
SRAM Memory (U43 & U44)
U43 and U44 are two 256 Kbyte x 16-bit asynchronous SRAM devices.
They are connected to the Stratix II device so they can be used by a
Nios® II embedded processor as general-purpose memory. The two 16-bit
devices can be used in parallel to implement a 32-bit wide memory
subsystem.
Table 19 lists the reference information for the SRAM memory.
Table 19. SRAM Memory Reference
Item
Description
Board reference
U43, U44
IDT71V416S10PH
SRAM Memory
IDT
Part Number
Device description
Manufacturer
Manufacturer web site
www.idt.com
26
Altera Corporation
Preliminary
ALTERA [ ALTERA CORPORATION ]
