Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–27
PLL Reconfiguration
Figure 5–20 shows how to adjust PLL counter settings dynamically by shifting their
new settings into a serial shift register chain or scan chain. Serial data shifts to the scan
chain via the scandataport, and shift registers are clocked by scanclk. The maximum
scanclkfrequency is 100 MHz. After shifting the last bit of data, asserting the
configupdatesignal for at least one scanclkclock cycle synchronously updates the
PLL configuration bits with the data in the scan registers.
Figure 5–20. PLL Reconfiguration Scan Chain
F
VCO
from M counter
from N counter
PFD
LF/K/CP
VCO
scandata
scanclkena
configupdate
inclk
/C4
/C3
/C2
/C1
/C0
/M
/N
scandataout
scandone
scanclk
1
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, not all counters update simultaneously.
To reconfigure the PLL counters, perform the following steps:
1. The scanclkenasignal is asserted at least one scanclkcycle prior to shifting in the
first bit of scandata Dn).
(
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
scanclk
.
3. After all 144 bits have been scanned into the scan chain, the scanclkenasignal is
deasserted to prevent inadvertent shifting of bits in the scan chain.
4. The configupdatesignal is asserted for one scanclkcycle to update the PLL
counters with the contents of the scan chain.
5. The scandonesignal goes high indicating that the PLL is being reconfigured. A
falling edge indicates that the PLL counters have been updated with new settings.
6. Reset the PLL using the aresetsignal if you make any changes to the M, N,
post-scale output C counters, or the
ICP , R, C settings.
7. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
