Chapter 3: Memory Blocks in the Cyclone III Device Family
3–3
Overview
Control Signals
The clock-enable control signal controls the clock entering the input and output
registers and the entire M9K memory block. This signal disables the clock so that the
M9K memory block does not see any clock edges and does not perform any
operations.
The rdenand wrencontrol signals control the read and write operations for each port
of M9K memory blocks. You can disable the rdenor wrensignals independently to
save power whenever the operation is not required.
Figure 3–1 shows how the register clock, clear, and control signals are implemented in
the Cyclone III device family M9K memory block.
Figure 3–1. M9K Control Signal Selection
Dedicated
Row LAB
Clocks
6
Local
Interconnect
clocken_b
clock_b
rden_b
addressstall_b
wren_b
aclr_b
byteena_b
rden_a
wren_a
clock_a
clocken_a
aclr_a
addressstall_a
byteena_a
Parity Bit Support
Parity checking for error detection is possible with the parity bit along with internal
logic resources. The Cyclone III device family M9K memory blocks support a parity
bit for each storage byte. You can use this bit as either a parity bit or as an additional
data bit. No parity function is actually performed on this bit.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
