Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–67
Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 2 of 4)
User
Mode
Configuration
Scheme
Pin Name
Pin Type
Description
Active-low chip enable. The nCEpin activates the Cyclone III
device family with a low signal to allow configuration. The
nCEpin must be held low during configuration, initialization,
and user-mode. In a single-device configuration, it must be
tied low. In a multi-device configuration, nCEof the first
device is tied low while its nCEOpin is connected to the nCE
pin of the next device in the chain. The nCEpin must also be
held low for successful JTAG programming of the device.
nCE
N/A
All
Input
Output that drives low when configuration is complete. In a
single-device configuration, you can leave this pin floating or
use it as a user I/O pin after configuration. In a multi-device
configuration, this pin feeds the nCEpin of the next device.
The nCEOof the last device in the chain is left floating or is
used as a user I/O pin after configuration.
N/A if
option is
on. I/O if
option is
off.
Output open
drain
nCEO
All
If you use the nCEOpin to feed the nCEpin of the next device,
use an external 10-k pull-up resistor to pull the nCEOpin
high to the VCCIO voltage of its I/O bank to help the internal
weak pull-up resistor.
If you use the nCEOpin as a user I/O pin after configuration,
set the state of the pin on the Dual-Purpose Pin settings.
Output control signal from the Cyclone III device family to the
serial configuration device in AS mode that enables the
configuration device. This pin functions as the nCSOpin in AS
mode and the FLASH_NCEpin in AP mode.
FLASH_nCE
,
(3)
I/O
AS, AP
Output
(1), (2)
Output control signal from the Cyclone III device to the
parallel flash in AP mode that enables the flash. Connects to
nCSO
(3)
the CE#pin on the Micron P30 or P33 flash.
This pin has an internal pull-up resistor that is always active.
In PS and FPP configuration, DCLKis the clock input used to
clock data from an external source into the target Cyclone III
device family. Data is latched into the device on the rising
edge of DCLK.
In AS mode, DCLKis an output from the Cyclone III device
family that provides timing for the configuration interface, it
has an internal pull-up resistor (typically 25 k) that is
always active.
Input (PS,
PS, FPP, AS,
In AP mode, DCLKis an output from the Cyclone III device
(1), (2)
DCLK
N/A
FPP).Output
(3)
(3)
AP
that provides timing for the configuration interface.
(AS, AP (3)
)
In active configuration schemes (AS or AP), this pin will be
driven into an inactive state after configuration completes.
Alternatively, in active schemes, you can use this pin as a
user I/O during user mode. In passive schemes (PS or FPP)
that use a control host, DCLKmust be driven either high or
low, whichever is more convenient. In passive schemes, you
cannot use DCLKas a user I/O in user mode. Toggling this pin
after configuration does not affect the configured device
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
