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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Cyclone III Device Family Overview  
1–9  
Cyclone III Device Family Architecture  
f
For more information, refer to the High-Speed Differential Interfaces in the Cyclone III  
Device Family chapter.  
Auto-Calibrating External Memory Interfaces  
Cyclone III device family supports common memory types such as DDR, DDR2,  
SDR SDRAM, and QDRII SRAM. DDR2 SDRAM memory interfaces support data  
rates up to 400 Mbps for Cyclone III devices and 333 Mbps for Cyclone III LS devices.  
Memory interfaces are supported on all sides of Cyclone III device family. Cyclone III  
device family has the OCT, DDR output registers, and 8-to-36-bit programmable DQ  
group widths features to enable rapid and robust implementation of different  
memory standards.  
An auto-calibrating megafunction is available in the Quartus II software for DDR and  
QDR memory interface PHYs. This megafunction is optimized to take advantage of  
the Cyclone III device family I/O structure, simplify timing closure requirements, and  
take advantage of the Cyclone III device family PLL dynamic reconfiguration feature  
to calibrate PVT changes.  
f
For more information, refer to the External Memory Interfaces in the Cyclone III Device  
Family chapter.  
Support for Industry-Standard Embedded Processors  
To quickly and easily create system-level designs using Cyclone III device family, you  
can select among the ×32-bit soft processor cores: Freescale®V1 Coldfire, ARM®  
Cortex M1, or Altera Nios® II, along with a library of 50 other IP blocks when using  
the system-on-a-programmable-chip (SOPC) Builder tool. SOPC Builder is an Altera  
Quartus II design tool that facilitates system-integration of IP blocks in an FPGA  
design. The SOPC Builder automatically generates interconnect logic and creates a  
testbench to verify functionality, saving valuable design time.  
Cyclone III device family expands the peripheral set, memory, I/O, or performance of  
legacy embedded processors. Single or multiple Nios II embedded processors are  
designed into Cyclone III device family to provide additional co-processing power, or  
even replace legacy embedded processors in your system. Using the Cyclone III  
device family and Nios II together provide low-cost, high-performance embedded  
processing solutions, which in turn allow you to extend the life cycle of your product  
and improve time-to-market over standard product solutions.  
1
Separate licensing of the Freescale and ARM embedded processors are required.  
Hot Socketing and Power-On-Reset  
Cyclone III device family features hot socketing (also known as hot plug-in or hot  
swap) and power sequencing support without the use of external devices. You can  
insert or remove a board populated with one or more Cyclone III device family  
during a system operation without causing undesirable effects to the running system  
bus or the board that was inserted into the system.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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