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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family  
9–37  
Configuration Features  
In a multi-device PS configuration, the nCEpin of the first device is connected to GND  
while its nCEOpin is connected to the nCEpin of the next device in the chain. The nCE  
input of the last device comes from the previous device, while its nCEOpin is left  
floating. After the first device completes configuration in a multi-device configuration  
chain, its nCEOpin drives low to activate the nCEpin of the second device, which  
prompts the second device to begin configuration. The second device in the chain  
begins configuration in one clock cycle. Therefore, the transfer of data destinations is  
transparent to the external host device. All other configuration pins (nCONFIG  
,
nSTATUS, DCLK,  
DATA[0], and CONF_DONE) are connected to every device in the chain.  
Configuration signals can require buffering to ensure signal integrity and prevent  
clock skew problems. Ensure that the DCLKand DATAlines are buffered. Because all  
device CONF_DONEpins are tied together, all devices initialize and enter user mode at  
the same time.  
If any device detects an error, configuration stops for the entire chain and the entire  
chain must be reconfigured because all nSTATUSand CONF_DONEpins are tied together.  
For example, if the first device flags an error on nSTATUS, it resets the chain by pulling  
its nSTATUSpin low. This behavior is similar to a single device detecting an error.  
You can have multiple devices that contain the same configuration data in your  
system. To support this configuration scheme, all device nCEinputs are tied to GND,  
while the nCEOpins are left floating. All other configuration pins (nCONFIG  
DATA[0], and CONF_DONE) are connected to every device in the chain.  
Configuration signals can require buffering to ensure signal integrity and prevent  
, nSTATUS,  
DCLK  
,
clock skew problems. Ensure that the DCLKand DATAlines are buffered. Devices must  
be of the same density and package. All devices start and complete configuration at  
the same time.  
August 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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