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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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9–20  
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family  
Configuration Features  
Altera recommends putting a buffer before the DATAand DCLKoutput from the master  
device to avoid signal strength and integrity issues. The buffer must not significantly  
change the DATA-to-DCLKrelationships or delay them with respect to other AS signals  
(ASDIand nCS). Also, the buffer must only drive the slave devices to ensure that the  
timing between the master device and the serial configuration device is unaffected.  
This configuration method supports both compressed and uncompressed .sofs.  
Therefore, if the configuration bitstream size exceeds the capacity of a serial  
configuration device, you can enable the compression feature in the .sof or you can  
select a larger serial configuration device.  
Guidelines for Connecting Serial Configuration Device to Cyclone III Device  
Family on AS Interface  
For single- and multi-device AS configurations, the board trace length and loading  
between the supported serial configuration device and Cyclone III device family must  
follow the recommendations listed in Table 9–9.  
Table 9–9. Maximum Trace Length and Loading for the AS Configuration  
Cyclone III  
Device Family  
AS Pins  
Maximum Board Trace Length from the  
Cyclone III Device Family to the Serial  
Configuration Device (Inches)  
Maximum Board Load (pF)  
DCLK  
DATA[0]  
nCSO  
10  
10  
10  
10  
15  
30  
30  
30  
ASDO  
Estimating AS Configuration Time  
AS configuration time is dominated by the time it takes to transfer data from the serial  
configuration device to the Cyclone III device family. This serial interface is clocked  
by the Cyclone III device family DCLKoutput (generated from an internal oscillator).  
Equation 9–2 and Equation 9–3 show the configuration time estimation for the  
Cyclone III device family.  
Equation 9–2.  
maximum DCLK period  
----------------------------------------------------------------  
Size   
= estimated maximum configuration ti  
1 bit  
Equation 9–3.  
50 ns  
1 bit  
------------  
3,500,000 bits   
= 175 ms  
To estimate the typical configuration time, use the typical DCLKperiod shown in  
Figure 9–7 on page 9–22. With a typical DCLKperiod of 33.33 ns, the typical  
configuration time is 116.7 ms. Enabling compression reduces the amount of  
configuration data that is sent to the Cyclone III device family, which also reduces  
configuration time. On average, compression reduces configuration time by 50%.  
Cyclone III Device Handbook  
Volume 1  
August 2012 Altera Corporation  
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