9–8
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
The output resistance of the repeater buffers must fit the maximum overshoot
equation shown in Equation 9–1:
(1)
Equation 9–1.
0.8Z R 1.8Z
O
E
O
Note to Equation 9–1:
(1) ZO is the transmission line impedance and RE is the equivalent resistance of the output buffer.
Configuration Process
This section describes the configuration process.
f
For more information about the configuration cycle state machine of Altera FPGAs,
refer to the Configuring Altera FPGAs chapter in volume 1 of the Configuration
Handbook.
Power Up
If the device is powered up from the power-down state, the VCCIO for all the I/O
banks must be powered up to the appropriate level for the device to exit POR.
To begin configuration, the required voltages listed in Table 9–4 must be powered up
to the appropriate voltage levels.
Table 9–4. Power-Up Voltage for Cyclone III Device Family Configuration
(1)
Device
Cyclone III
Voltage that must be Powered-Up
(2)
VCCINT, VCCA, VCCIO
(2)
Cyclone III LS
Notes to Table 9–4:
VCCBAT, VCCINT, VCCA, VCCIO
(1) Voltages must be powered up to the appropriate voltage levels to begin configuration.
(2) VCCIO is for banks in which the configuration and JTAG pins reside.
Reset
When nCONFIGor nSTATUSis low, the device is in reset. After power-up, the Cyclone III
device family goes through POR. POR delay depends on the MSEL pin settings,
which correspond to your configuration scheme.
Depending on the configuration scheme, a fast or standard POR time is available.
POR time for fast POR ranges between 3–9 ms. POR time for standard POR, which
has a lower power-ramp rate, ranges between 50–200 ms.
During POR, the device resets, holds nSTATUSand CONF_DONElow, and tri-states all
user I/O pins.
1
The configuration bus is not tri-stated in POR stage if the MSELpins are set to AS or AP
mode. To tri-state the configuration bus for AS and AP configuration schemes, you
must tie nCEhigh and nCONFIGlow. For more information about the hardware
implementation, refer to “Configuring With Multiple Bus Masters” on page 9–30.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
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